Description

Nanotechnology will provide enormous amounts of computing resources in a very small footprint.  This Independent Study will explore potential architectures for high performance computing that will be able to exploit massively parallel computing resources made available by Nanotechnology.  Research will include some background research on past and existing parallel computing environments and will focus on finding the most suitable computer architectures for utilizing the vast amount of computing resources which are expected to be made available by Nanotechnology. This project may potentially include simulations focusing on automatic parallelization strategies for reconfigurable computing architecture(s) such as the Cell Matrix and FPGA configurations.

Project Schedule

References

[1] Paul Beckett, Andrew Jennings, “Towards Nanocomputer Architecture”, Proceedings of the seventh Asia-Pacific conference on Computer systems architecture - Volume 6, Melbourne, Victoria, Australia, 141 – 150, 2002, Australian Computer Society, Inc. Darlinghurst, Australia 

[2] Lisa J Durbeck and Nicholas J Macias, “The Cell Matrix: an architecture for nanocomputing”, Eighth Foresight Conference on Molecular Technology, November 3-5, 2000 Institute of Physics Publishing Aug 2001 

[3]  Lisa J Durbeck and Nicholas J Macias, “Self-Assembling Circuits with Autonomous Fault Handling”, Proceedings of the 2002 NASA/DoD Conference on Evolvable Hardware (EH'02), Page: 46, IEEE Computer Society  Washington, DC, USA  2002  

[4] Zhi Guo, Walid Najjar, Frank Vahid, Kees Vissers, “A Quantitative Analysis of the Speedup Factors of FPGAs over Processors”, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, 162 – 170, ACM Press   New York, NY, USA 2004 

[6] Lisa J.K. Durbeck, Nicholas J. Macias, “Defect-tolerant, fine-grained parallel testing of a Cell Matrix”, in Proceedings of SPIE ITCom 2002 Series, Vol. 4867 Copyright© 2002 SPIE

[7] D Crawley, K, Nickolic, M Forshaw, 3D Nanoelectronic Computer Architecture and Implementation, Bristol and Philadelphia: IOP Publishing LTD, 2005.

[8] Charles P. Poole Jr., Frank J. Owens, Introduction to Nanotechnology, Hoboken, New Jersey: John Wiley and Sons, Inc., 2003.

[9] Nicholas J. Macias, “The PIG Paradigm: The Design and Use of a Massively Parallel Fine Grained Self-Reconfigurable Infinitely Scalable Architecture”, in Proceedings of the First NASA/DoD Workshop on Evolvable Hardware Copyright© 1999 IEEE

[10] Stamatis Vassiliadis,Stephan Wong, Georgi Gaydadjiev, Koen Bertels, Georgi Kuzmanov, Elena Moscu Panainte, "The MOLEN Polymorphic Processor," IEEE TRANSACTIONS ON COMPUTERS, vol. 53, no. 11, pp. 1363-1375 , November 2004.

[11] D. Burger, S.W. Keckler, K.S. McKinley, Kathryn S. McKinley, Mike Dahlin, Lizy K. John, Calvin Lin, Charles R.Moore, James Burrill, Robert G.McDonald, WilliamYoder, "Scaling to the End of Silicon with EDGE Architectures", IEEE Computer, vol 37, num 7, pp. 44-55, July, 2004.

[12] Jack Dongarra, Thomas Sterling, Horst Simon, Erich Strohmaier, "High-performance computing: clusters, constellations, MPPs, and future directions," IEEE Computational Science and Engineering, vol. 7, no. 2, pp. 51- 59, March-April 2005.

[13] James M. Baker Jr., Brian Gold, Mark Bucciero, Sidney Bennett , Rajneesh Mahajan, Priyadarshini Ramachandran, Jignesh Shah, " SCMP: A Single-Chip Message-Passing Parallel Computer," The Journal of Supercomputing, vol. 30, no. 2, pp. 133 -149 , November 2004.

[14] Sotirios G. Ziavras, Qian Wang, Paraskevi Papathanasiou, " Viable Architectures for High-Performance Computing," The Computer Journal, vol. 46, no. 1, pp. 36-54, Jan 2003.

[16] John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, 3 ed. , San Francisco, CA USA: Morgan Kaufmann Publishers, 2003. 

[17] Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore, “Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture”, in Proceedings of the Annual International Symposium on Computer Architecture, pp. 422-433, June 2003.  

[18] "25th Edition of TOP500 List of World’s Fastest Supercomputers Released: DOE/LLNL BlueGene/L and IBM gain Top Positions" [Online document] Jun 22, 2005, Available at http://www.top500.org/news/articles/article_68.php

[19] B. Culbertson, R. Amerson, R. Carter, P. Kuekes, G. Snider, ”Defect Tolerance on the Teramac Custom Computer”, in Proceedings of the 1997 IEEE Symposium on FPGA's for Custom Computing Machines, pp. 116-123.

[20] João M. P. Cardoso and Mário P. Véstias, “Architectures and Compilers to Support Reconfigurable Computing” [Online Document] 1999, Available at http://www.acm.org/crossroads/xrds5-3/rcconcept.html

[21] C. Chang, J. Wawrzynek,R.W. Brodersen, " BEE2: a high-end reconfigurable computing system," Design & Test of Computers, IEEE, vol. 22, no. 2, pp. 114-125, March-April 2005.  

[22] Dan Reed, "Is There Light at the End of the Tunnel? ," IEEE Computational Science and Engineering, vol. 7, no. 2, pp. 51- 59, March-April 2005.

[23] [2005 Nov], “Downloadable Cell Matrix Software”, Available at http://www.cellmatrix.com/entryway/products/software/software.html 

[24] [2005 Nov], “Free Open Source IP cores and chip design website”, Available at http://www.opencores.org/

[25] [2005 Nov], “Diameter of an Atom”, Available at http://hypertextbook.com/facts/MichaelPhillip.shtml

updated 12/14/05